1. Field of the Invention
The invention relates to flash memory. More particularly, the present invention relates to a flash memory structure with increased capacitive-coupling ratio and a method for fabricating the flash memory.
2. Description of the Related Art
Nonvolatile memory devices are extensively used in modern electronic equipment to store data. Recently, xe2x80x9cFlashxe2x80x9d memory devices, a particular type of semiconductor nonvolatile memory, have been increasingly developed and used in portable equipment such as hand-held computers or digital still cameras.
Because electronic products evolve to miniaturized devices with higher density, flash memory devices consequently must be denser and have high capacitive-coupling ratio. Increasing the storage capacity of the flash memory requires a reduction in the size of the memory cell to improve its density. This reduction is conventionally accomplished by decreasing the gate length of the memory cell as well as the data line pitch. However, a minimum lithographic feature size imposed by lithographic processes during the manufacture of the flash memory conventionally limits this dimensional reduction.
On the other hand, high capacitive-coupling ratio is required because it allows for lower internal voltage operation. However, a high capacitive-coupling ratio may be contradictory with the requirement to have denser memory device because a reduction of the gate length decreases the surface area of the floating gate and consequently the capacitive-coupling ratio of the memory cell.
A method for fabricating a flash memory cell know in the art is described hereafter. The flash memory is fabricated from a conventional a gate stack. The conventional gate stack comprises a tunneling oxide layer, first floating gate layer, polysilicon layer, insulating layer, spacer polysilicon layer and cap layer successively formed and patterned on a substrate. Source/drain regions are formed in the substrate adjacent to the gate structure. A pair of spacers are formed on the sidewalls of the gate stack and on the source/drain regions. Isolation structures are fabricated by filling a plurality of trenches formed through the source/drain regions with chemical vapor deposition (CVD) of silicon dioxide and boron phosphosilicate glass (BPSG). The cap layer, spacer polysilicon, and insulating layer then are removed and a second floating gate layer is formed on the first floating gate layer. By providing a 3D-shaped second floating gate layer, the capacitive-coupling ratio of the floating gate, constituted of the first and second floating gate layers, is increased.
The foregoing method is complex because it requires numerous steps, and the capacitive-coupling ratio still can be improved.
An aspect of the present invention is to provide a method for fabricating a memory cell having increased capacitive-coupling ratio.
To accomplish at least the above objectives, the present invention provides a method for fabricating a memory cell that comprises the following steps. A gate stack is formed on a substrate, the gate stack comprises a stack of tunneling dielectric layer, first conductive layer, and a cap layer. Source and drain regions are formed in the substrate adjacent to the gate stack. A plurality of spacers are formed on sidewalls of the gate stack. A portion of the substrate is selectively removed to form a plurality of trenches through the source and drain regions. A first dielectric layer is formed over the substrate to fill the trenches. In an embodiment, material of the first dielectric is for example the same as the material of the cap layer and different from the material of the spacers. The first dielectric layer and the cap layer thus can be concurrently removed by a selective etching until the first conductor layer is exposed. As a result, a plurality of trench isolation structures are formed with a down set surface. In another embodiment, the first dielectric layer and the cap layer are necessary to be the same material and are independently removed. As a result, the cap layer is removed and a top portion of the first dielectric layer filled in the trench is removed. A second conductive layer is blanket deposited over the substrate and patterned, such that the patterned second conductive layer extends over the isolation structures but separates from the adjacent one. Due to the down set surface of the trench isolation structures, the second conductive layer extends over the outer side surface of the spacer to the surface of the trench isolation structure. The surface area of the floating gate, which includes the first conductive layer and the patterned second conductive layer, is hence increased. A second dielectric layer and a third conductive layer are sequentially formed over the substrate, wherein the third conductive layer forms a control gate.
The present invention further provides a memory cell structure that increases the capacitve-coupling ratio. The memory cell structure of the present invention comprises the following elements. A gate stack on a substrate comprises a tunneling dielectric and a floating gate. Source/drain regions are located in the substrate, adjacent to the gate stack. A plurality of spacers are formed on the sidewalls of the gate stack and on the source/drain regions. An isolation structure located in the substrate to isolate the gate stack, wherein the isolation structure is also raised up to the spacers but is lower than the top of the spacers. A conductive layer is located over a topographic surface over the floating gate, an exposed portion of the spacer, and a portion of the trench isolation structure. As a result, the conductive layer serve together with the floating gate. The conductive layer increases the effective area of the floating gate and therefore at least increase the capacitive-coupling ratio.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.